VLSI Chip Design Hands on using open source EDA
Prospective Experts:
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8 th – 12th July 2019 Local Coordinator: |
Course contents:
VLSI design, SoC Design : Generic digital design flow, hierarchical design representation,
Platform based SoC design
Floorplanning & timing analysis: Floorplanning and pre layout timing analysis [OpenSTA]
Placement, Clock tree synthesis: Partitioning, iterative placement, analytical placement, Wire-length
estimation; Clock tree synthesis [MAGIC tool]
Global routing, Detailed routing: Maze routing, line probe algorithms; Left edge, dog-leg, algorithms;
Signal integrity, DRC, LVS, ECO; post layout STA
[Orouter, MAGIC tool]
Analog and Mixed Signal Circuit
Specifications to Design: Important aspects, particular to Analog IC design Flow; Introduction
and distinctions between discrete time and continuous time designs;
Example design with basics of sampling, effect of noise in sample
and hold circuits; Brief introduction and design of OPAMP, and multistage OPAMPs
Analog and Mixed Signal
Circuits Layout to GDS: Dealing with frequency compensations, noise and non-linearity in a
multi-stage OPAMP; OPAMP offset cancellation techniques;
Switched capacitor Circuits Specification to Design
Registration Fee and Accommodation:
Faculty and Research Scholars (PhD): Nil and free accommodation on sharing basis.
Others:Rs 3000 and extra nominal charges for accommodation and food.
Core Team Members, E&ICT Academy:
Prof Aparajita Ojha
Email: aojha@iiitdmj.ac.in
Prof. Vijay Kumar Gupta
Email: vkgupta@iiitdmj.ac.in
Prof. P.N. Kondekar
Email: pnkondekar@iiitdmj.ac.in
Dr. Atul Gupta
Email: atul@iiitdmj.ac.in
Dr. Prashant Kumar Jain
Email: pkjain@iiitdmj.ac.in
Website: ict.iiitdmj.ac.in
Contact us :
Prof. P.N. Kondekar : +9425805445, 0761-2794461
Electronics and ICT Academy
PDPM Indian Institute of Information Technology,
Design and Manufacturing, Jabalpur,
Dumna Airport Road, Jabalpur 482005
Email: pnkondekar@iiitdmj.ac.in
Website: ict.iiitdmj.ac.in